PATH: //opt/alt/python311/share/doc/alt-python311-pyparsing-doc/examples/verilog
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[ .. KEMBALI ]
📄 Ctr3sr.v
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📄 INIT
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📄 RANDOM_GATE
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📄 RANDOM_INTERCONNECT
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📄 SEED
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📄 TestCtr3sr.v
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📄 addacc.v
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📄 addacc1_dro.v
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📄 addacc1_t1ff.v
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📄 addacc_conf.v
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📄 addacc_dro.v
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📄 addacc_t1ff.v
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📄 allParseOutput.zip
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📄 and.v
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📄 and_gate.v
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📄 conf.v
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📄 core_test.v
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📄 count2bit.v
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📄 count_all_prims_test.v
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📄 count_loads_test.v
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📄 dds.v
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📄 diff_udp.v
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📄 display_all_nets_test.v
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📄 div16.v
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📄 dro.v
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📄 dro1_cell.v
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📄 dro_cell.v
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📄 dump_and_fill_mem_test.v
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📄 exprinfo_test.v
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📄 fetch_values_test.v
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📄 ff.v
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📄 ff_test.v
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📄 fifo.v
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📄 find_driver.tcl.gz
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📄 framer.v
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📄 func_72bit_test.v
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📄 gen.v
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📄 gencrc.v
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📄 gzip.exe
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📄 hadd.v
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📁 hasCompilerDirectives/
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📄 hello_test.v
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📄 in_port.v
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📄 inv.v
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📄 inv_cell.v
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📄 invoke_commands_test.v
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📄 invoke_options_test.v
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📄 jtl2.v
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📄 jutzi
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📄 list_cells_test.v
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📄 list_nets_test.v
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📄 list_parameters_test.v
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📄 list_path_delays_test.v
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📄 list_pathout_ports_test.v
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📄 list_prim_delays_test.v
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📄 load_in.v
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📄 load_out.v
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📄 mem_arb.v
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📄 mipd_delays_test.v
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📄 mult16.v
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📄 multi21_udp.v
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📄 my_monitor1_test.v
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📄 my_monitor2_test.v
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📄 my_monitor_test.v
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📄 my_strobe_test.v
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📄 myram64x16.v
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📄 nco.v
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📄 ndro.v
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📁 new/
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📁 new2/
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📄 nodeinfo_test.v
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📄 onehot.v
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📄 or.v
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📄 out_port.v
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📁 parseOutput/
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📄 pic.v
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📄 pipe1.v
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📄 pipe2.v
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📄 pl.v
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📄 pli_handbook_examples_pc.zip
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📄 port_info_test.v
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📄 pow_test.v
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📄 primitives.v
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📄 propagatep_test.v
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📄 psr1.v
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📄 psr1_conf.v
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📄 psr1_dro.v
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📄 psr1_split.v
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📄 psr2.v
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📄 psr2_and.v
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📄 psr2_split.v
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📄 read_4state_value_test.v
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📄 read_attribute_test.v
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📄 read_delays_test.v
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📄 read_stimulus_short_test.v
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📄 read_stimulus_test.v
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📄 read_strengthval_test.v
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📄 read_test_vector_test.v
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📄 read_timeval_test.v
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📄 read_vector_test.v
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📄 read_vecval_test.v
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📄 realpow_test.v
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📄 rf.v
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📄 sci_alu_comb_calltf_shell.v
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📄 sci_alu_comb_calltf_test.v
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📄 sci_alu_comb_misctf_shell.v
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📄 sci_alu_comb_misctf_test.v
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📄 sci_alu_combinational_shell.v
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📄 sci_alu_combinational_test.v
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📄 sci_alu_latched_shell.v
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📄 sci_alu_latched_test.v
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📄 sci_alu_sequential_shell.v
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📄 sci_alu_sequential_test.v
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📄 sci_alu_synchronized_shell.v
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📄 sci_alu_synchronized_test.v
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📄 sci_alu_with_delays_shell.v
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📄 sci_alu_with_delays_test.v
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📄 set_mipd_delays_test.v
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📄 show_all_nets_test.v
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📄 show_all_signals1_test.v
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📄 show_all_signals2_test.v
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📄 show_all_signals3_test.v
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📄 show_all_signals_1_test.v
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📄 show_all_signals_2_test.v
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📄 show_all_signals_3_test.v
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📄 show_value_test.v
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📄 sig_gen.v
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📄 simple_core.v
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📄 splitter.v
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📄 sqrt32.v
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📄 sqrt8m.v
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📄 sr_nv_ctf.v
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📄 srcnt.v
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📄 string.v
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📄 t1ff.v
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📄 testcase.v
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📄 testcase2.v
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📄 testcase4.v
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📄 testcase5.v
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📄 tff.v
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📄 timescale_info_test.v
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📄 usb.v
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📄 use_workarea_test.v
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📄 utmi_if.v
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📄 vpi_utilities_test.v
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📄 wb.v
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📄 wpulse.v
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📄 xor.v
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📄 zzzexample.v
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SAVING...
BERHASIL DIUBAH!
EDITING: utmi_if.v
///////////////////////////////////////////////////////////////////// //// //// //// UTMI Interface //// //// //// //// //// //// Author: Rudolf Usselmann //// //// rudi@asics.ws //// //// //// //// //// //// Downloaded from: http://www.opencores.org/cores/usb/ //// //// //// ///////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Rudolf Usselmann //// //// rudi@asics.ws //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer.//// //// //// //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// //// POSSIBILITY OF SUCH DAMAGE. //// //// //// ///////////////////////////////////////////////////////////////////// // CVS Log // // $Id: utmi_if.v,v 1.0 2001/03/07 09:17:12 rudi Exp $ // // $Date: 2001/03/07 09:17:12 $ // $Revision: 1.0 $ // $Author: rudi $ // $Locker: $ // $State: Exp $ // // Change History: // $Log: utmi_if.v,v $ // Revision 1.0 2001/03/07 09:17:12 rudi // // // Changed all revisions to revision 1.0. This is because OpenCores CVS // interface could not handle the original '0.1' revision .... // // Revision 0.2 2001/03/07 09:08:13 rudi // // Added USB controll signaling (Line Status) block. Fixed some minor // typos, added resume bit and signal. // // Revision 0.1.0.1 2001/02/28 08:11:45 rudi // Initial Release // // `include "usb_defines.v" module utmi_if( // UTMI Interface (EXTERNAL) phy_clk, rst, DataOut, TxValid, TxReady, RxValid, RxActive, RxError, DataIn, XcvSelect, TermSel, SuspendM, LineState, OpMode, usb_vbus, // Internal Interface rx_data, rx_valid, rx_active, rx_err, tx_data, tx_valid, tx_valid_last, tx_ready, tx_first, // Misc Interfaces mode_hs, usb_reset, usb_suspend, usb_attached, resume_req ); input phy_clk; output rst; output [7:0] DataOut; output TxValid; input TxReady; input [7:0] DataIn; input RxValid; input RxActive; input RxError; output XcvSelect; output TermSel; output SuspendM; input [1:0] LineState; output [1:0] OpMode; input usb_vbus; output [7:0] rx_data; output rx_valid, rx_active, rx_err; input [7:0] tx_data; input tx_valid; input tx_valid_last; output tx_ready; input tx_first; output mode_hs; // High Speed Mode output usb_reset; // USB Reset output usb_suspend; // USB Suspend output usb_attached; // Attached to USB input resume_req; /////////////////////////////////////////////////////////////////// // // Local Wires and Registers // reg [7:0] rx_data; reg rx_valid, rx_active, rx_err; reg [7:0] DataOut; reg tx_ready; reg TxValid; wire drive_k; /////////////////////////////////////////////////////////////////// // // Misc Logic // /////////////////////////////////////////////////////////////////// // // RX Interface Input registers // always @(posedge phy_clk) if(!rst) rx_valid <= #1 0; else rx_valid <= #1 RxValid; always @(posedge phy_clk) if(!rst) rx_active <= #1 0; else rx_active <= #1 RxActive; always @(posedge phy_clk) if(!rst) rx_err <= #1 0; else rx_err <= #1 RxError; always @(posedge phy_clk) rx_data <= #1 DataIn; /////////////////////////////////////////////////////////////////// // // TX Interface Output/Input registers // wire tx_valid_sr; assign tx_valid_sr = (!rst) ? 0 : tx_valid_last ? 1 : TxReady ? 0 : tx_valid_sr; always @(posedge phy_clk) if(TxReady | tx_first) DataOut <= #1 tx_data; else if(drive_k) DataOut <= #1 8'hff; always @(posedge phy_clk) tx_ready <= #1 TxReady; always @(posedge phy_clk) TxValid <= #1 tx_valid | tx_valid_sr | drive_k; /////////////////////////////////////////////////////////////////// // // Line Status Signaling & Speed Negotiation Block // utmi_ls u0( .clk( phy_clk ), .rst( rst ), .resume_req( resume_req ), .rx_active( rx_active ), .tx_ready( tx_ready ), .drive_k( drive_k ), .XcvSelect( XcvSelect ), .TermSel( TermSel ), .SuspendM( SuspendM ), .LineState( LineState ), .OpMode( OpMode ), .usb_vbus( usb_vbus ), .mode_hs( mode_hs ), .usb_reset( usb_reset ), .usb_suspend( usb_suspend ), .usb_attached( usb_attached ) ); endmodule
SIMPAN PERUBAHAN