MASTER_V67

PATH: //opt/alt/python311/share/doc/alt-python311-pyparsing-doc/examples/verilog

[ .. KEMBALI ]

📄 RANDOM_GATE

📄 RANDOM_INTERCONNECT

📄 TestCtr3sr.v

📄 addacc1_dro.v

📄 addacc1_t1ff.v

📄 addacc_conf.v

📄 addacc_dro.v

📄 addacc_t1ff.v

📄 allParseOutput.zip

📄 and_gate.v

📄 core_test.v

📄 count2bit.v

📄 count_all_prims_test.v

📄 count_loads_test.v

📄 diff_udp.v

📄 display_all_nets_test.v

📄 dro1_cell.v

📄 dro_cell.v

📄 dump_and_fill_mem_test.v

📄 exprinfo_test.v

📄 fetch_values_test.v

📄 find_driver.tcl.gz

📄 func_72bit_test.v

📁 hasCompilerDirectives/

📄 hello_test.v

📄 inv_cell.v

📄 invoke_commands_test.v

📄 invoke_options_test.v

📄 list_cells_test.v

📄 list_nets_test.v

📄 list_parameters_test.v

📄 list_path_delays_test.v

📄 list_pathout_ports_test.v

📄 list_prim_delays_test.v

📄 load_out.v

📄 mipd_delays_test.v

📄 multi21_udp.v

📄 my_monitor1_test.v

📄 my_monitor2_test.v

📄 my_monitor_test.v

📄 my_strobe_test.v

📄 myram64x16.v

📄 nodeinfo_test.v

📄 out_port.v

📁 parseOutput/

📄 pli_handbook_examples_pc.zip

📄 port_info_test.v

📄 pow_test.v

📄 primitives.v

📄 propagatep_test.v

📄 psr1_conf.v

📄 psr1_dro.v

📄 psr1_split.v

📄 psr2_and.v

📄 psr2_split.v

📄 read_4state_value_test.v

📄 read_attribute_test.v

📄 read_delays_test.v

📄 read_stimulus_short_test.v

📄 read_stimulus_test.v

📄 read_strengthval_test.v

📄 read_test_vector_test.v

📄 read_timeval_test.v

📄 read_vector_test.v

📄 read_vecval_test.v

📄 realpow_test.v

📄 sci_alu_comb_calltf_shell.v

📄 sci_alu_comb_calltf_test.v

📄 sci_alu_comb_misctf_shell.v

📄 sci_alu_comb_misctf_test.v

📄 sci_alu_combinational_shell.v

📄 sci_alu_combinational_test.v

📄 sci_alu_latched_shell.v

📄 sci_alu_latched_test.v

📄 sci_alu_sequential_shell.v

📄 sci_alu_sequential_test.v

📄 sci_alu_synchronized_shell.v

📄 sci_alu_synchronized_test.v

📄 sci_alu_with_delays_shell.v

📄 sci_alu_with_delays_test.v

📄 set_mipd_delays_test.v

📄 show_all_nets_test.v

📄 show_all_signals1_test.v

📄 show_all_signals2_test.v

📄 show_all_signals3_test.v

📄 show_all_signals_1_test.v

📄 show_all_signals_2_test.v

📄 show_all_signals_3_test.v

📄 show_value_test.v

📄 simple_core.v

📄 splitter.v

📄 sr_nv_ctf.v

📄 testcase.v

📄 testcase2.v

📄 testcase3.v

📄 testcase4.v

📄 testcase5.v

📄 timescale_info_test.v

📄 use_workarea_test.v

📄 vpi_utilities_test.v

📄 zzzexample.v

SAVING...

BERHASIL DIUBAH!

EDITING: show_all_signals1_test.v

/**********************************************************************
 * $show_all_signals example -- Verilog test bench source code
 *
 * Verilog test bench to test the $show_all_signals PLI application on
 * a 1-bit adder modeled using RTL code.
 *
 * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
 *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
 *   Contact: www.wkap.il
 *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
 *   Contact: www.sutherland.com or (503) 692-0898
 *********************************************************************/
`timescale 1ns / 1ns
module top;
  integer    test;
  tri  [1:0] results;

addbit i1 (test[0], test[1], test[2], results[0], results[1]);

initial
    begin
      test = 3'b000;
      #10 test = 3'b001;

#10 $show_all_signals1(top);
      #10 $show_all_signals1(i1);

#10 $stop;
      #10 $finish;
    end
endmodule

/*** An RTL level 1 bit adder model ***/
`timescale 1ns / 1ns
module addbit (a, b, ci, sum, co);
  input  a, b, ci;
  output sum, co;

wire  a, b, ci;
  reg   sum, co;

always @(a or b or ci)
    {co, sum} = a + b + ci;

endmodule
/*********************************************************************/