PATH: //opt/alt/python311/share/doc/alt-python311-pyparsing-doc/examples/verilog
FILE_BARU
CREATE
FOLDER_BARU
MKDIR
UPLOAD_FILE
GO
[ .. KEMBALI ]
📄 Ctr3sr.v
↓
X
📄 INIT
↓
X
📄 RANDOM_GATE
↓
X
📄 RANDOM_INTERCONNECT
↓
X
📄 SEED
↓
X
📄 TestCtr3sr.v
↓
X
📄 addacc.v
↓
X
📄 addacc1_dro.v
↓
X
📄 addacc1_t1ff.v
↓
X
📄 addacc_conf.v
↓
X
📄 addacc_dro.v
↓
X
📄 addacc_t1ff.v
↓
X
📄 allParseOutput.zip
↓
X
📄 and.v
↓
X
📄 and_gate.v
↓
X
📄 conf.v
↓
X
📄 core_test.v
↓
X
📄 count2bit.v
↓
X
📄 count_all_prims_test.v
↓
X
📄 count_loads_test.v
↓
X
📄 dds.v
↓
X
📄 diff_udp.v
↓
X
📄 display_all_nets_test.v
↓
X
📄 div16.v
↓
X
📄 dro.v
↓
X
📄 dro1_cell.v
↓
X
📄 dro_cell.v
↓
X
📄 dump_and_fill_mem_test.v
↓
X
📄 exprinfo_test.v
↓
X
📄 fetch_values_test.v
↓
X
📄 ff.v
↓
X
📄 ff_test.v
↓
X
📄 fifo.v
↓
X
📄 find_driver.tcl.gz
↓
X
📄 framer.v
↓
X
📄 func_72bit_test.v
↓
X
📄 gen.v
↓
X
📄 gencrc.v
↓
X
📄 gzip.exe
↓
X
📄 hadd.v
↓
X
📁 hasCompilerDirectives/
X
📄 hello_test.v
↓
X
📄 in_port.v
↓
X
📄 inv.v
↓
X
📄 inv_cell.v
↓
X
📄 invoke_commands_test.v
↓
X
📄 invoke_options_test.v
↓
X
📄 jtl2.v
↓
X
📄 jutzi
↓
X
📄 list_cells_test.v
↓
X
📄 list_nets_test.v
↓
X
📄 list_parameters_test.v
↓
X
📄 list_path_delays_test.v
↓
X
📄 list_pathout_ports_test.v
↓
X
📄 list_prim_delays_test.v
↓
X
📄 load_in.v
↓
X
📄 load_out.v
↓
X
📄 mem_arb.v
↓
X
📄 mipd_delays_test.v
↓
X
📄 mult16.v
↓
X
📄 multi21_udp.v
↓
X
📄 my_monitor1_test.v
↓
X
📄 my_monitor2_test.v
↓
X
📄 my_monitor_test.v
↓
X
📄 my_strobe_test.v
↓
X
📄 myram64x16.v
↓
X
📄 nco.v
↓
X
📄 ndro.v
↓
X
📁 new/
X
📁 new2/
X
📁 new3/
X
📄 nodeinfo_test.v
↓
X
📄 onehot.v
↓
X
📄 or.v
↓
X
📄 out_port.v
↓
X
📁 parseOutput/
X
📄 pic.v
↓
X
📄 pipe1.v
↓
X
📄 pipe2.v
↓
X
📄 pl.v
↓
X
📄 pli_handbook_examples_pc.zip
↓
X
📄 port_info_test.v
↓
X
📄 pow_test.v
↓
X
📄 primitives.v
↓
X
📄 propagatep_test.v
↓
X
📄 psr1.v
↓
X
📄 psr1_conf.v
↓
X
📄 psr1_dro.v
↓
X
📄 psr1_split.v
↓
X
📄 psr2.v
↓
X
📄 psr2_and.v
↓
X
📄 psr2_split.v
↓
X
📄 read_4state_value_test.v
↓
X
📄 read_attribute_test.v
↓
X
📄 read_delays_test.v
↓
X
📄 read_stimulus_short_test.v
↓
X
📄 read_stimulus_test.v
↓
X
📄 read_strengthval_test.v
↓
X
📄 read_test_vector_test.v
↓
X
📄 read_timeval_test.v
↓
X
📄 read_vector_test.v
↓
X
📄 read_vecval_test.v
↓
X
📄 realpow_test.v
↓
X
📄 rf.v
↓
X
📄 sci_alu_comb_calltf_shell.v
↓
X
📄 sci_alu_comb_calltf_test.v
↓
X
📄 sci_alu_comb_misctf_shell.v
↓
X
📄 sci_alu_comb_misctf_test.v
↓
X
📄 sci_alu_combinational_shell.v
↓
X
📄 sci_alu_combinational_test.v
↓
X
📄 sci_alu_latched_shell.v
↓
X
📄 sci_alu_latched_test.v
↓
X
📄 sci_alu_sequential_shell.v
↓
X
📄 sci_alu_sequential_test.v
↓
X
📄 sci_alu_synchronized_shell.v
↓
X
📄 sci_alu_synchronized_test.v
↓
X
📄 sci_alu_with_delays_shell.v
↓
X
📄 sci_alu_with_delays_test.v
↓
X
📄 set_mipd_delays_test.v
↓
X
📄 show_all_nets_test.v
↓
X
📄 show_all_signals1_test.v
↓
X
📄 show_all_signals2_test.v
↓
X
📄 show_all_signals3_test.v
↓
X
📄 show_all_signals_1_test.v
↓
X
📄 show_all_signals_2_test.v
↓
X
📄 show_all_signals_3_test.v
↓
X
📄 show_value_test.v
↓
X
📄 sig_gen.v
↓
X
📄 simple_core.v
↓
X
📄 splitter.v
↓
X
📄 sqrt32.v
↓
X
📄 sqrt8m.v
↓
X
📄 sr_nv_ctf.v
↓
X
📄 srcnt.v
↓
X
📄 string.v
↓
X
📄 t1ff.v
↓
X
📄 testcase.v
↓
X
📄 testcase2.v
↓
X
📄 testcase3.v
↓
X
📄 testcase4.v
↓
X
📄 testcase5.v
↓
X
📄 tff.v
↓
X
📄 timescale_info_test.v
↓
X
📄 usb.v
↓
X
📄 use_workarea_test.v
↓
X
📄 utmi_if.v
↓
X
📄 vpi_utilities_test.v
↓
X
📄 wb.v
↓
X
📄 wpulse.v
↓
X
📄 xor.v
↓
X
📄 zzzexample.v
↓
X
SAVING...
BERHASIL DIUBAH!
EDITING: mem_arb.v
///////////////////////////////////////////////////////////////////// //// //// //// Memory Buffer Arbiter //// //// Arbitrates between the internal DMA and external bus //// //// interface for the internal buffer memory //// //// //// //// Author: Rudolf Usselmann //// //// rudi@asics.ws //// //// //// //// //// //// Downloaded from: http://www.opencores.org/cores/usb/ //// //// //// ///////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Rudolf Usselmann //// //// rudi@asics.ws //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer.//// //// //// //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// //// POSSIBILITY OF SUCH DAMAGE. //// //// //// ///////////////////////////////////////////////////////////////////// // CVS Log // // $Id: mem_arb.v,v 1.0 2001/03/07 09:17:12 rudi Exp $ // // $Date: 2001/03/07 09:17:12 $ // $Revision: 1.0 $ // $Author: rudi $ // $Locker: $ // $State: Exp $ // // Change History: // $Log: mem_arb.v,v $ // Revision 1.0 2001/03/07 09:17:12 rudi // // // Changed all revisions to revision 1.0. This is because OpenCores CVS // interface could not handle the original '0.1' revision .... // // Revision 0.1.0.1 2001/02/28 08:10:52 rudi // Initial Release // // `include "usb_defines.v" module mem_arb( phy_clk, wclk, rst, // SSRAM Interface radr, rdin, rdout, rre, rwe, // IDMA Memory Interface madr, mdout, mdin, mwe, mreq, mack, // WISHBONE Memory Interface wadr, wdout, wdin, wwe, wreq, wack ); input phy_clk, wclk, rst; output [14:0] radr; input [31:0] rdin; output [31:0] rdout; output rre, rwe; input [14:0] madr; output [31:0] mdout; input [31:0] mdin; input mwe; input mreq; output mack; input [14:0] wadr; output [31:0] wdout; input [31:0] wdin; input wwe; input wreq; output wack; /////////////////////////////////////////////////////////////////// // // Local Wires and Registers // wire wsel; reg [14:0] radr; reg [31:0] rdout; reg rwe; reg mack; reg mack_r; wire mcyc; reg wack; wire wcyc; reg wwe_r; /////////////////////////////////////////////////////////////////// // // Memory Arbiter Logic // // IDMA has always first priority // ----------------------------------------- // Ctrl Signals assign wsel = (wreq | wcyc) & !mreq; // ----------------------------------------- // SSRAM Specific // Data Path always @(wsel or wdin or mdin) if(wsel) rdout = wdin; else rdout = mdin; // Address Path always @(wsel or wadr or madr) if(wsel) radr = wadr; else radr = madr; // Write Enable Path always @(wsel or wwe_r or mwe or mcyc or wcyc) if(wsel) rwe = wwe_r & wcyc; else rwe = mwe & mcyc; assign rre = 1; // ----------------------------------------- // IDMA specific assign mdout = rdin; always @(mreq) mack = mreq; always @(posedge phy_clk) mack_r <= #1 mack; assign mcyc = mack; // Qualifier for writes // ----------------------------------------- // WISHBONE specific assign wdout = rdin; reg wack_d, wack_r; always @(wack_d or mreq) wack = wack_d & !mreq; always @(posedge phy_clk) wack_r <= #1 wack_d; always @(wreq or mreq) if(!mreq) wack_d = wreq; else wack_d = 0; always @(posedge phy_clk) wwe_r <= #1 wwe; assign wcyc = wack_d | wack_r; // Qualifier for writes endmodule
SIMPAN PERUBAHAN