MASTER_V67

PATH: //opt/alt/python311/share/doc/alt-python311-pyparsing-doc/examples/verilog

[ .. KEMBALI ]

📄 RANDOM_GATE

📄 RANDOM_INTERCONNECT

📄 TestCtr3sr.v

📄 addacc1_dro.v

📄 addacc1_t1ff.v

📄 addacc_conf.v

📄 addacc_dro.v

📄 addacc_t1ff.v

📄 allParseOutput.zip

📄 and_gate.v

📄 core_test.v

📄 count2bit.v

📄 count_all_prims_test.v

📄 count_loads_test.v

📄 diff_udp.v

📄 display_all_nets_test.v

📄 dro1_cell.v

📄 dro_cell.v

📄 dump_and_fill_mem_test.v

📄 exprinfo_test.v

📄 fetch_values_test.v

📄 find_driver.tcl.gz

📄 func_72bit_test.v

📁 hasCompilerDirectives/

📄 hello_test.v

📄 inv_cell.v

📄 invoke_commands_test.v

📄 invoke_options_test.v

📄 list_cells_test.v

📄 list_nets_test.v

📄 list_parameters_test.v

📄 list_path_delays_test.v

📄 list_pathout_ports_test.v

📄 list_prim_delays_test.v

📄 load_out.v

📄 mipd_delays_test.v

📄 multi21_udp.v

📄 my_monitor1_test.v

📄 my_monitor2_test.v

📄 my_monitor_test.v

📄 my_strobe_test.v

📄 myram64x16.v

📄 nodeinfo_test.v

📄 out_port.v

📁 parseOutput/

📄 pli_handbook_examples_pc.zip

📄 port_info_test.v

📄 pow_test.v

📄 primitives.v

📄 propagatep_test.v

📄 psr1_conf.v

📄 psr1_dro.v

📄 psr1_split.v

📄 psr2_and.v

📄 psr2_split.v

📄 read_4state_value_test.v

📄 read_attribute_test.v

📄 read_delays_test.v

📄 read_stimulus_short_test.v

📄 read_stimulus_test.v

📄 read_strengthval_test.v

📄 read_test_vector_test.v

📄 read_timeval_test.v

📄 read_vector_test.v

📄 read_vecval_test.v

📄 realpow_test.v

📄 sci_alu_comb_calltf_shell.v

📄 sci_alu_comb_calltf_test.v

📄 sci_alu_comb_misctf_shell.v

📄 sci_alu_comb_misctf_test.v

📄 sci_alu_combinational_shell.v

📄 sci_alu_combinational_test.v

📄 sci_alu_latched_shell.v

📄 sci_alu_latched_test.v

📄 sci_alu_sequential_shell.v

📄 sci_alu_sequential_test.v

📄 sci_alu_synchronized_shell.v

📄 sci_alu_synchronized_test.v

📄 sci_alu_with_delays_shell.v

📄 sci_alu_with_delays_test.v

📄 set_mipd_delays_test.v

📄 show_all_nets_test.v

📄 show_all_signals1_test.v

📄 show_all_signals2_test.v

📄 show_all_signals3_test.v

📄 show_all_signals_1_test.v

📄 show_all_signals_2_test.v

📄 show_all_signals_3_test.v

📄 show_value_test.v

📄 simple_core.v

📄 splitter.v

📄 sr_nv_ctf.v

📄 testcase.v

📄 testcase2.v

📄 testcase3.v

📄 testcase4.v

📄 testcase5.v

📄 timescale_info_test.v

📄 use_workarea_test.v

📄 vpi_utilities_test.v

📄 zzzexample.v

SAVING...

BERHASIL DIUBAH!

EDITING: testcase.v

`timescale 1ns/1ps

module mult_piped_8x8_2sC (a, b, clk, reset, y);

input[7:0] a,b;
input clk,reset;
output[15:0] y;

//--------------------------------------
  // Function: always @ posedge clk       
  //   y(t=0) = a(t-8) * b(t-8)           
  //                                      
  // Simulation: PASSED                   
  // Synthesis: Needs re-timing feature in
  //            synthesis tool            
  //                                      
  //--------------------------------------

reg[7:0] aR[8:0];
reg[7:0] bR[8:0];
reg[15:0] yR[8:0];

always @ (posedge clk) // pipeline_stages
  begin
   aR[7] = aR[6];  // pipeline things
   bR[7] = bR[6];
   yR[7] = yR[6];
   aR[6] = aR[5];
   bR[6] = bR[5];
   yR[6] = yR[5];
   aR[5] = aR[4];
   bR[5] = bR[4];
   yR[5] = yR[4];
   aR[4] = aR[3];
   bR[4] = bR[3];
   yR[4] = yR[3];
   aR[3] = aR[2];
   bR[3] = bR[2];
   yR[3] = yR[2];
   aR[2] = aR[1];
   bR[2] = bR[1];
   yR[2] = yR[1];
   aR[1] = aR[0];
   bR[1] = bR[0];
   yR[1] = yR[0];
   aR[0] = a;
   bR[0] = b;
            // multiply result (a*b) appears after +clk
   yR[0] = multiply_8x8_2sC (aR[0],bR[0]);
  end

function[15:0] multiply_8x8_2sC;
input[7:0] a,b;
reg[7:0] a_mag,b_mag;
reg[14:0] y_mag;
reg[14:0] y_neg;
begin
  case (a[7])
   0: a_mag = a[6:0];
   1: a_mag = 128 - a[6:0];        // max(a_mag) = 128, thus 8 bits
  endcase
  case (b[7])
    0: b_mag = b[6:0];
    1: b_mag = 128 - b[6:0];
  endcase
  y_mag = a_mag * b_mag;            // max(y_mag) = 16384, thus 15 bits
  if ((a[7] ^ b[7]) & (y_mag != 0)) // if (a * b) is -ve AND non-zero
  begin                             // y_mag >=1, <= 16256, thus need only 14 bits
    y_neg = 32768 - y_mag[13:0];    // max(y_neg) = 32767, thus need 15 bits
    multiply_8x8_2sC = {1'b1,y_neg}; 
  end
  else
   multiply_8x8_2sC = y_mag;
end
endfunction

assign y = multiply_8x8_2sC (a,b); // un_pipelined_output
assign y = yR[7];

endmodule