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[ .. KEMBALI ]
📄 a.out.h
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📄 acct.h
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📄 acrn.h
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📄 adb.h
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📄 adfs_fs.h
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📄 affs_hardblocks.h
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📄 agpgart.h
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📄 aio_abi.h
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📄 am437x-vpfe.h
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📁 android/
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📄 apm_bios.h
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📄 arcfb.h
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📄 arm_sdei.h
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📄 aspeed-lpc-ctrl.h
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📄 aspeed-p2a-ctrl.h
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📄 atalk.h
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📄 atm.h
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📄 atm_eni.h
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📄 atm_he.h
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📄 atm_idt77105.h
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📄 atmarp.h
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📄 atmbr2684.h
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📄 atmdev.h
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📄 atmioc.h
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📄 atmlec.h
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📄 atmmpc.h
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📄 atmppp.h
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📄 atmsap.h
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📄 atmsvc.h
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📄 audit.h
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📄 auto_dev-ioctl.h
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📄 auto_fs.h
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📄 auto_fs4.h
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📄 auxvec.h
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📄 ax25.h
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📄 batadv_packet.h
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📄 batman_adv.h
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📄 baycom.h
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📄 bcm933xx_hcs.h
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📄 bfs_fs.h
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📄 binfmts.h
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📄 bits.h
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📄 blkpg.h
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📄 blktrace_api.h
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📄 blkzoned.h
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📄 bpf.h
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📄 bpf_common.h
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📄 bpf_perf_event.h
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📄 bpfilter.h
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📄 bpqether.h
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📄 bsg.h
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📄 bt-bmc.h
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📄 btf.h
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📁 byteorder/
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📄 cciss_ioctl.h
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📄 ccs.h
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📄 cdrom.h
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📄 cec-funcs.h
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📄 cec.h
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📄 cfm_bridge.h
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📄 chio.h
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📁 cifs/
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📄 close_range.h
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📄 cm4000_cs.h
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📄 coda.h
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📄 coff.h
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📄 connector.h
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📄 const.h
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📄 coresight-stm.h
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📄 cramfs_fs.h
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📄 cryptouser.h
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📄 cuda.h
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📄 cxl_mem.h
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📄 cycx_cfm.h
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📄 dcbnl.h
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📄 dccp.h
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📄 devlink.h
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📄 dlm.h
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📄 dlm_device.h
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📄 dlm_netlink.h
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📄 dlm_plock.h
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📄 dlmconstants.h
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📄 dm-ioctl.h
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📄 dm-log-userspace.h
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📄 dma-buf.h
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📄 dma-heap.h
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📄 dn.h
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📄 dns_resolver.h
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📄 dpll.h
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📄 dqblk_xfs.h
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📁 dvb/
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📄 edd.h
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📄 efs_fs_sb.h
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📄 elf-fdpic.h
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📄 elf.h
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📄 errno.h
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📄 errqueue.h
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📄 erspan.h
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📄 ethtool.h
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📄 ethtool_netlink.h
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📄 ethtool_netlink_generated.h
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📄 eventfd.h
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📄 eventpoll.h
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📄 f2fs.h
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📄 fb.h
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📄 fcntl.h
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📄 fib_rules.h
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📄 fiemap.h
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📄 filter.h
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📄 firewire-cdev.h
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📄 fou.h
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📄 fs.h
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📄 fsi.h
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📄 fsl_hypervisor.h
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📄 fsl_mc.h
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📄 fuse.h
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📄 futex.h
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📄 gameport.h
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📄 gen_stats.h
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📁 genwqe/
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📄 gfs2_ondisk.h
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📄 gpio.h
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📄 gsmmux.h
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📄 gtp.h
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📄 handshake.h
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📄 hash_info.h
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📁 hdlc/
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📄 hdlc.h
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📄 hdlcdrv.h
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📄 hdreg.h
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📄 hid.h
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📄 hiddev.h
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📄 hidraw.h
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📄 hpet.h
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📁 hsi/
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📄 hsr_netlink.h
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📄 hw_breakpoint.h
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📄 hyperv.h
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📄 i2c-dev.h
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📄 i2c.h
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📄 i2o-dev.h
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📄 i8k.h
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📄 icmp.h
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📄 icmpv6.h
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📄 idxd.h
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📄 if.h
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📄 if_addr.h
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📄 if_addrlabel.h
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📄 if_alg.h
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📄 if_arcnet.h
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📄 if_arp.h
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📄 if_bonding.h
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📄 if_bridge.h
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📄 if_cablemodem.h
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📄 if_eql.h
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📄 if_ether.h
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📄 if_fc.h
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📄 if_fddi.h
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📄 if_hippi.h
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📄 if_infiniband.h
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📄 if_link.h
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📄 if_ltalk.h
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📄 if_macsec.h
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📄 if_packet.h
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📄 if_phonet.h
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📄 if_plip.h
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📄 if_ppp.h
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📄 if_pppol2tp.h
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📄 if_pppox.h
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📄 if_slip.h
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📄 if_team.h
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📄 if_tun.h
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📄 if_tunnel.h
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📄 if_vlan.h
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📄 if_x25.h
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📄 if_xdp.h
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📄 igmp.h
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📁 iio/
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📄 ila.h
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📄 in.h
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📄 in6.h
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📄 in_route.h
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📄 inet_diag.h
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📄 inotify.h
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📄 input-event-codes.h
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📄 input.h
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📄 io_uring.h
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📄 ioctl.h
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📄 iommufd.h
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📄 ioprio.h
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📄 ip.h
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📄 ip6_tunnel.h
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📄 ip_vs.h
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📄 ipc.h
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📄 ipmi.h
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📄 ipmi_bmc.h
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📄 ipmi_msgdefs.h
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📄 ipmi_ssif_bmc.h
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📄 ipsec.h
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📄 ipv6.h
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📄 ipv6_route.h
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📄 ipx.h
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📄 irqnr.h
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📁 isdn/
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📄 iso_fs.h
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📄 isst_if.h
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📄 ivtv.h
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📄 ivtvfb.h
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📄 jffs2.h
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📄 joystick.h
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📄 kcm.h
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📄 kcmp.h
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📄 kcov.h
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📄 kd.h
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📄 kdev_t.h
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📄 kernel-page-flags.h
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📄 kernel.h
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📄 kernelcapi.h
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📄 kexec.h
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📄 keyboard.h
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📄 keyctl.h
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📄 kfd_ioctl.h
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📄 kfd_sysfs.h
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📄 kvm.h
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📄 kvm_para.h
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📄 l2tp.h
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📄 landlock.h
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📄 libc-compat.h
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📄 limits.h
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📄 lirc.h
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📄 llc.h
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📄 loadpin.h
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📄 loop.h
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📄 lp.h
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📄 lsm.h
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📄 lwtunnel.h
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📄 magic.h
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📄 major.h
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📄 map_to_7segment.h
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📄 matroxfb.h
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📄 max2175.h
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📄 mdio.h
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📄 media-bus-format.h
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📄 media.h
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📄 mei.h
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📄 mei_uuid.h
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📄 membarrier.h
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📄 memfd.h
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📄 mempolicy.h
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📄 meye.h
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📄 mii.h
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📄 minix_fs.h
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📁 misc/
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📄 mman.h
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📁 mmc/
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📄 mmtimer.h
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📄 module.h
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📄 mount.h
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📄 mpls.h
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📄 mpls_iptunnel.h
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📄 mptcp.h
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📄 mptcp_pm.h
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📄 mqueue.h
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📄 mroute.h
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📄 mroute6.h
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📄 mrp_bridge.h
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📄 msdos_fs.h
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📄 msg.h
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📄 mshv.h
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📄 mtio.h
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📄 nbd-netlink.h
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📄 nbd.h
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📄 ncsi.h
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📄 ndctl.h
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📄 neighbour.h
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📄 net.h
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📄 net_dropmon.h
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📄 net_namespace.h
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📄 net_shaper.h
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📄 net_tstamp.h
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📄 netconf.h
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📄 netdev.h
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📄 netdevice.h
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📁 netfilter/
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📄 netfilter.h
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📁 netfilter_arp/
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📄 netfilter_arp.h
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📁 netfilter_bridge/
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📄 netfilter_bridge.h
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📄 netfilter_decnet.h
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📁 netfilter_ipv4/
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📄 netfilter_ipv4.h
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📁 netfilter_ipv6/
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📄 netfilter_ipv6.h
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📄 netlink.h
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📄 netlink_diag.h
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📄 netrom.h
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📄 nexthop.h
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📄 nfc.h
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📄 nfs.h
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📄 nfs2.h
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📄 nfs3.h
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📄 nfs4.h
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📄 nfs4_mount.h
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📄 nfs_fs.h
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📄 nfs_idmap.h
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📄 nfs_mount.h
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📄 nfsacl.h
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📁 nfsd/
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📄 nfsd_netlink.h
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📄 nilfs2_api.h
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📄 nilfs2_ondisk.h
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📄 nitro_enclaves.h
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📄 nl80211.h
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📄 nsfs.h
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📄 nubus.h
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📄 nvme_ioctl.h
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📄 nvram.h
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📄 omap3isp.h
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📄 omapfb.h
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📄 oom.h
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📄 openat2.h
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📄 openvswitch.h
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📄 packet_diag.h
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📄 param.h
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📄 parport.h
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📄 patchkey.h
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📄 pci.h
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📄 pci_regs.h
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📄 pcitest.h
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📄 perf_event.h
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📄 personality.h
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📄 pfkeyv2.h
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📄 pfrut.h
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📄 pg.h
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📄 phantom.h
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📄 phonet.h
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📄 pidfd.h
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📄 pkt_cls.h
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📄 pkt_sched.h
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📄 pktcdvd.h
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📄 pmu.h
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📄 poll.h
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📄 posix_acl.h
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📄 posix_acl_xattr.h
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📄 posix_types.h
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📄 ppdev.h
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📄 ppp-comp.h
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📄 ppp-ioctl.h
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📄 ppp_defs.h
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📄 pps.h
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📄 pr.h
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📄 prctl.h
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📄 psample.h
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📄 psci.h
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📄 psp-dbc.h
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📄 psp-sev.h
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📄 ptp_clock.h
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📄 ptrace.h
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📄 qemu_fw_cfg.h
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📄 qnx4_fs.h
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📄 qnxtypes.h
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📄 qrtr.h
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📄 quota.h
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📄 radeonfb.h
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📁 raid/
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📄 random.h
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📄 rds.h
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📄 reboot.h
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📄 reiserfs_fs.h
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📄 reiserfs_xattr.h
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📄 remoteproc_cdev.h
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📄 resource.h
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📄 rfkill.h
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📄 rio_cm_cdev.h
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📄 rio_mport_cdev.h
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📄 rkisp1-config.h
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📄 romfs_fs.h
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📄 rose.h
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📄 route.h
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📄 rpl.h
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📄 rpl_iptunnel.h
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📄 rpmsg.h
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📄 rpmsg_types.h
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📄 rseq.h
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📄 rtc.h
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📄 rtnetlink.h
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📄 rxrpc.h
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📄 scc.h
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📁 sched/
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📄 sched.h
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📄 scif_ioctl.h
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📄 screen_info.h
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📄 sctp.h
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📄 seccomp.h
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📄 securebits.h
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📄 sed-opal.h
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📄 seg6.h
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📄 seg6_genl.h
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📄 seg6_hmac.h
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📄 seg6_iptunnel.h
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📄 seg6_local.h
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📄 selinux_netlink.h
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📄 sem.h
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📄 serial.h
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📄 serial_core.h
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📄 serial_reg.h
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📄 serio.h
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📄 sev-guest.h
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📄 shm.h
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📄 signal.h
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📄 smc.h
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📄 smc_diag.h
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📄 smiapp.h
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📄 snmp.h
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📄 sock_diag.h
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📄 socket.h
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📄 sockios.h
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📄 sonet.h
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📄 sonypi.h
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📁 spi/
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📄 stat.h
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📄 stddef.h
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📄 string.h
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📁 sunrpc/
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📄 suspend_ioctls.h
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📄 swab.h
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📄 switchtec_ioctl.h
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📄 sync_file.h
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📄 synclink.h
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📄 sysctl.h
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📄 sysinfo.h
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📄 target_core_user.h
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📄 taskstats.h
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📁 tc_act/
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📁 tc_ematch/
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📄 tcp.h
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📄 tcp_metrics.h
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📄 tdx-guest.h
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📄 tee.h
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📄 termios.h
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📄 thermal.h
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📄 timerfd.h
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📄 times.h
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📄 timex.h
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SAVING...
BERHASIL DIUBAH!
EDITING: fpga-dfl.h
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Header File for FPGA DFL User API * * Copyright (C) 2017-2018 Intel Corporation, Inc. * * Authors: * Kang Luwei <luwei.kang@intel.com> * Zhang Yi <yi.z.zhang@intel.com> * Wu Hao <hao.wu@intel.com> * Xiao Guangrong <guangrong.xiao@linux.intel.com> */ #ifndef _LINUX_FPGA_DFL_H #define _LINUX_FPGA_DFL_H #include <linux/types.h> #include <linux/ioctl.h> #define DFL_FPGA_API_VERSION 0 /* * The IOCTL interface for DFL based FPGA is designed for extensibility by * embedding the structure length (argsz) and flags into structures passed * between kernel and userspace. This design referenced the VFIO IOCTL * interface (include/uapi/linux/vfio.h). */ #define DFL_FPGA_MAGIC 0xB6 #define DFL_FPGA_BASE 0 #define DFL_PORT_BASE 0x40 #define DFL_FME_BASE 0x80 /* Common IOCTLs for both FME and AFU file descriptor */ /** * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) * * Report the version of the driver API. * Return: Driver API Version. */ #define DFL_FPGA_GET_API_VERSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) /** * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) * * Check whether an extension is supported. * Return: 0 if not supported, otherwise the extension is supported. */ #define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) /* IOCTLs for AFU file descriptor */ /** * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0) * * Reset the FPGA Port and its AFU. No parameters are supported. * Userspace can do Port reset at any time, e.g. during DMA or PR. But * it should never cause any system level issue, only functional failure * (e.g. DMA or PR operation failure) and be recoverable from the failure. * Return: 0 on success, -errno of failure */ #define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0) /** * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1, * struct dfl_fpga_port_info) * * Retrieve information about the fpga port. * Driver fills the info in provided struct dfl_fpga_port_info. * Return: 0 on success, -errno on failure. */ struct dfl_fpga_port_info { /* Input */ __u32 argsz; /* Structure length */ /* Output */ __u32 flags; /* Zero for now */ __u32 num_regions; /* The number of supported regions */ __u32 num_umsgs; /* The number of allocated umsgs */ }; #define DFL_FPGA_PORT_GET_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1) /** * FPGA_PORT_GET_REGION_INFO - _IOWR(FPGA_MAGIC, PORT_BASE + 2, * struct dfl_fpga_port_region_info) * * Retrieve information about a device memory region. * Caller provides struct dfl_fpga_port_region_info with index value set. * Driver returns the region info in other fields. * Return: 0 on success, -errno on failure. */ struct dfl_fpga_port_region_info { /* input */ __u32 argsz; /* Structure length */ /* Output */ __u32 flags; /* Access permission */ #define DFL_PORT_REGION_READ (1 << 0) /* Region is readable */ #define DFL_PORT_REGION_WRITE (1 << 1) /* Region is writable */ #define DFL_PORT_REGION_MMAP (1 << 2) /* Can be mmaped to userspace */ /* Input */ __u32 index; /* Region index */ #define DFL_PORT_REGION_INDEX_AFU 0 /* AFU */ #define DFL_PORT_REGION_INDEX_STP 1 /* Signal Tap */ __u32 padding; /* Output */ __u64 size; /* Region size (bytes) */ __u64 offset; /* Region offset from start of device fd */ }; #define DFL_FPGA_PORT_GET_REGION_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2) /** * DFL_FPGA_PORT_DMA_MAP - _IOWR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3, * struct dfl_fpga_port_dma_map) * * Map the dma memory per user_addr and length which are provided by caller. * Driver fills the iova in provided struct afu_port_dma_map. * This interface only accepts page-size aligned user memory for dma mapping. * Return: 0 on success, -errno on failure. */ struct dfl_fpga_port_dma_map { /* Input */ __u32 argsz; /* Structure length */ __u32 flags; /* Zero for now */ __u64 user_addr; /* Process virtual address */ __u64 length; /* Length of mapping (bytes)*/ /* Output */ __u64 iova; /* IO virtual address */ }; #define DFL_FPGA_PORT_DMA_MAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3) /** * DFL_FPGA_PORT_DMA_UNMAP - _IOW(FPGA_MAGIC, PORT_BASE + 4, * struct dfl_fpga_port_dma_unmap) * * Unmap the dma memory per iova provided by caller. * Return: 0 on success, -errno on failure. */ struct dfl_fpga_port_dma_unmap { /* Input */ __u32 argsz; /* Structure length */ __u32 flags; /* Zero for now */ __u64 iova; /* IO virtual address */ }; #define DFL_FPGA_PORT_DMA_UNMAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4) /** * struct dfl_fpga_irq_set - the argument for DFL_FPGA_XXX_SET_IRQ ioctl. * * @start: Index of the first irq. * @count: The number of eventfd handler. * @evtfds: Eventfd handlers. */ struct dfl_fpga_irq_set { __u32 start; __u32 count; __s32 evtfds[]; }; /** * DFL_FPGA_PORT_ERR_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 5, * __u32 num_irqs) * * Get the number of irqs supported by the fpga port error reporting private * feature. Currently hardware supports up to 1 irq. * Return: 0 on success, -errno on failure. */ #define DFL_FPGA_PORT_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, \ DFL_PORT_BASE + 5, __u32) /** * DFL_FPGA_PORT_ERR_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 6, * struct dfl_fpga_irq_set) * * Set fpga port error reporting interrupt trigger if evtfds[n] is valid. * Unset related interrupt trigger if evtfds[n] is a negative value. * Return: 0 on success, -errno on failure. */ #define DFL_FPGA_PORT_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, \ DFL_PORT_BASE + 6, \ struct dfl_fpga_irq_set) /** * DFL_FPGA_PORT_UINT_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 7, * __u32 num_irqs) * * Get the number of irqs supported by the fpga AFU interrupt private * feature. * Return: 0 on success, -errno on failure. */ #define DFL_FPGA_PORT_UINT_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, \ DFL_PORT_BASE + 7, __u32) /** * DFL_FPGA_PORT_UINT_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 8, * struct dfl_fpga_irq_set) * * Set fpga AFU interrupt trigger if evtfds[n] is valid. * Unset related interrupt trigger if evtfds[n] is a negative value. * Return: 0 on success, -errno on failure. */ #define DFL_FPGA_PORT_UINT_SET_IRQ _IOW(DFL_FPGA_MAGIC, \ DFL_PORT_BASE + 8, \ struct dfl_fpga_irq_set) /* IOCTLs for FME file descriptor */ /** * DFL_FPGA_FME_PORT_PR - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 0, * struct dfl_fpga_fme_port_pr) * * Driver does Partial Reconfiguration based on Port ID and Buffer (Image) * provided by caller. * Return: 0 on success, -errno on failure. * If DFL_FPGA_FME_PORT_PR returns -EIO, that indicates the HW has detected * some errors during PR, under this case, the user can fetch HW error info * from the status of FME's fpga manager. */ struct dfl_fpga_fme_port_pr { /* Input */ __u32 argsz; /* Structure length */ __u32 flags; /* Zero for now */ __u32 port_id; __u32 buffer_size; __u64 buffer_address; /* Userspace address to the buffer for PR */ }; #define DFL_FPGA_FME_PORT_PR _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0) /** * DFL_FPGA_FME_PORT_RELEASE - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, * int port_id) * * Driver releases the port per Port ID provided by caller. * Return: 0 on success, -errno on failure. */ #define DFL_FPGA_FME_PORT_RELEASE _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, int) /** * DFL_FPGA_FME_PORT_ASSIGN - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, * int port_id) * * Driver assigns the port back per Port ID provided by caller. * Return: 0 on success, -errno on failure. */ #define DFL_FPGA_FME_PORT_ASSIGN _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, int) /** * DFL_FPGA_FME_ERR_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_FME_BASE + 3, * __u32 num_irqs) * * Get the number of irqs supported by the fpga fme error reporting private * feature. Currently hardware supports up to 1 irq. * Return: 0 on success, -errno on failure. */ #define DFL_FPGA_FME_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, \ DFL_FME_BASE + 3, __u32) /** * DFL_FPGA_FME_ERR_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 4, * struct dfl_fpga_irq_set) * * Set fpga fme error reporting interrupt trigger if evtfds[n] is valid. * Unset related interrupt trigger if evtfds[n] is a negative value. * Return: 0 on success, -errno on failure. */ #define DFL_FPGA_FME_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, \ DFL_FME_BASE + 4, \ struct dfl_fpga_irq_set) #endif /* _LINUX_FPGA_DFL_H */
SIMPAN PERUBAHAN